1. Field of the Invention
The present invention relates to a manufacturing method for an SOI semiconductor device, and more particularly to a manufacturing method for an SOI semiconductor device, which includes creating transistors and an element isolation region on an SOI substrate. The SOI substrate has a support substrate and a semiconductor layer formed on the support substrate via an insulation film. SOI stands for Silicon On Insulator.
2. Description of the Related Art
One of semiconductor devices which consume less power and operate at a high speed is an SOI semiconductor device. The SOI semiconductor device has an SOI substrate, and transistors and an element isolation region are created on a semiconductor layer of the SOI substrate. The SOI substrate has the semiconductor layer created on a support substrate made of silicon via an insulation film, such as buried oxide film. In a semiconductor manufacturing process, if down sizing (size reduction, miniaturization) should be achieved, the gate insulation film becomes thinner and devices with a high charging damage, such as a high density plasma CVD device and high density plasma etching device, must be used. As a result, the thin gate insulation film is exposed to the charging damage, the gate insulation film deteriorates, and the characteristics of the transistors deteriorate due to the insufficient withstand voltage of the gate insulation film and the generation of an interface level at the interface of the gate insulation film.
A conventional manufacturing method for an SOI semiconductor device is disclosed in, for example, Japanese Patent Application Kokai (Laid-Open Publication) No. 8-330250; particularly, page 5 and FIG. 1 are relevant. In this manufacturing method, a dummy pattern for shorting the gate interconnect to the support substrate is created together with the gate interconnect. Then, the dummy pattern is etched, and the gate interconnect and the support substrate are insulated.
In the manufacturing method according to Japanese Patent Application Kokai No. 8-330250, electric charges entered from the plasma to the gate interconnect during an etching process are released to the support substrate via the dummy interconnects, but Japanese Patent Application Kokai No. 8-330250 states nothing on the electric charges which enter the source/drain interconnect. It is assumed that since transistors are directly created on the support substrate, the electric charges in the source/drain interconnect can possibly be released from the source/drain region to the support substrate. In the SOI semiconductor device, however, the buried oxide film exists on the support substrate, so that the electric charges of the source/drain interconnect cannot be released to the support substrate; the electric charges are stored in the source/drain region. Because of this, a large potential difference is generated between the source/drain region and the gate electrode, that is, a large electric field is applied to the gate insulation film, and the gate insulation film receives the charging damage. In this case, the withstand voltage of the gate insulation film may deteriorate, and the characteristics of the transistors may deteriorate by the interface level, which is generated at the interface of the gate insulation film.